1. Field of the Invention
This invention relates generally to data processors. More particularly, this invention relates to a system and method for providing programmable hardware instruction traps in a microprocessor.
2. Description of Background Art
When designing a data processor it is important to rigorously test the design before tape-out. Generally, such testing attempts to identify errors in functional characteristics of the data processor. However, due to time limitations it is not always feasible to fully test all functional characteristics of the data processor design before tape-out. Tape-out occurs when the physical database design for manufacturing the parts, e.g., the data processor, is released.
Occasionally, functional errors in the design of the data processor are not discovered until after tape-out. In this circumstance it is expensive to correct the design and produce new data processor parts. Functional errors can also occur because of a flaw in manufacturing that effects certain instructions.
A related limitation occurs with superscalar central processing units (CPUs). Many software application programs are not developed for use in a superscalar environment. When a superscalar CPU executes instructions in such an application program some instructions may not perform in the manner they were designed.
What is needed is a system and method for providing a programmable hardware device within a CPU that permits a plurality of instructions to be trapped before they are executed. The instructions that are to be trapped are programmable to provide flexibility during CPU debugging and to ensure that a variety of application programs can be properly executed by the CPU. The system must also provide a means for permitting a trapped instruction to be emulated and/or to be executed serially.